It is important for a micro-processor unit (MPU) to support bus frequencies that are slower then the processor (MPU) frequency. This feature allows the design of systems with both a low frequency bus to maintain low cost and power and a high frequency processor for high performance, two clock functions are required.
To provide this feature, a method is needed to generate the processor clock, the bus clock and to set the processor to external bus clock relationship. It is desirable for this method to work across as wide a range of frequencies as possible. For today's MPUs, this can mean supporting processor frequencies from 100 MHz plus to near 0 Hz operation. External control of this operation can provide added flexibility.
There are several ways to provide the functionality described above. One is to use two unrelated clock generators of different frequency, the slower for the bus clock and the faster for the processor clock. Communication between the processor and the bus can be done by synchronizing the necessary signals between the processor and the bus. This method has the advantage of not fixing the processor to bus clock relationship. However, synchronization is normally accomplished by serially registering a signal from the driving frequency domain several times (at least two) in registers clocked at the frequency of receiving frequency domain. A performance penalty results from this added latency. Also, if the synchronization process is done on the MPU, both clocks must be present on the MPU.
A second way to provide the functionality described above is to generate two clocks with both a fixed frequency and a fixed phase relationship. This is normally accomplished by a phase locked loop (PLL) circuit. The higher frequency clock is used for the processor clock and the lower frequency is used in the bus control logic that interfaces to the external bus.
There are several design decisions and costs associated with this methodology. First, the phase relationship between the two clocks must be tightly controlled. This adds to the complexity and cost of the PLL. Second, PLLs can not operate over a large frequency range. This limits the application of this technique to this frequency range. Also, PLLs take time to achieve phase/frequency lock to the input reference. This means for systems that desire to stop the clocks for low power modes, there is a time penalty to restart the clocks to allow the PLL to achieve steady-state operation.
If the PLL design is left to the system designer, then the part must input both the bus and processor clock. Careful attention is needed to insure that the clock distribution networks inside the MPU do not create excessive skew between these clocks. If the PLL is put on the MPU, then the MPU designer is faced with designing the PLL. A PLL requires different circuit design techniques and considerations than normal digital circuits and must be carefully isolated from other circuits on the chip for correct operation of both the PLL and the digital MPU logic.
All the above solutions have costs, complexities and/or operational restrictions. The current invention provides the desired functions and operating frequencies with lower costs and complexities and without operation frequency restrictions.